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introduction_to_digital_systems:sequential_logic [2024/12/10 12:15] – [6.2.3 Medvedev Machine] mexleadminintroduction_to_digital_systems:sequential_logic [2024/12/17 09:37] (current) – mexleadmin
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   * The **output vector** $\vec{Y}$ represents the $l$ outputs $Y_0 ... Y_{l-1}$.   * The **output vector** $\vec{Y}$ represents the $l$ outputs $Y_0 ... Y_{l-1}$.
   * The **state vector** $\vec{Z}$ represents the $m$ inputs $Z_0 ... Z_{m-1}$.   * The **state vector** $\vec{Z}$ represents the $m$ inputs $Z_0 ... Z_{m-1}$.
-  * The sign $(n)$ or $n$ marking the current point in time and therefore e.g. the current state $Z_0(n)$. +  * The subscript $(n)$ or $n$ marking the current point in time and therefore e.g. the current state $Z_0(n)$. 
-  * The sign $(n+1)$ or $n+1$ marking the next upcoming point in time and therefore e.g. the next state $Z_0(n+1)$.+  * The subscript $(n+1)$ or $n+1$ marking the next upcoming point in time and therefore e.g. the next state $Z_0(n+1)$.
   * Sequential logic circuits are also called **Finite State Machines** (FSM) or sometimes also shortened to "state machines".   * Sequential logic circuits are also called **Finite State Machines** (FSM) or sometimes also shortened to "state machines".