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electrical_engineering_and_electronics_1:block08 [2025/10/24 19:48] mexleadminelectrical_engineering_and_electronics_1:block08 [2025/10/24 20:35] (aktuell) mexleadmin
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   * Combine transforms to reduce complex resistive networks to an **unloaded / loaded divider** and to size $R_{\rm L}$ for given performance goals (tie-in to Block 07 figures).   * Combine transforms to reduce complex resistive networks to an **unloaded / loaded divider** and to size $R_{\rm L}$ for given performance goals (tie-in to Block 07 figures).
 </callout> </callout>
 +
 +~~PAGEBREAK~~ ~~CLEARFIX~~
 +===== Preparation at Home =====
 +
 +And again: 
 +  * Please read through the following chapter.
 +  * Also here, there are some clips for more clarification under 'Embedded resources'
 +
 +For checking your understanding please do the following exercise:
 +  * 4.5.3
 +
  
 ===== 90-minute plan ===== ===== 90-minute plan =====