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electrical_engineering_and_electronics_1:block08 [2025/10/20 03:08] – mexleadminelectrical_engineering_and_electronics_1:block08 [2025/10/24 20:35] (aktuell) – mexleadmin
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-====== Block 08 — Two-port theory and transforms ======+====== Block 08 — Two-terminal theory and transforms ======
  
 <callout> <WRAP> <imgcaption imageNo1 | examples for networks> </imgcaption> {{drawio>Beispiele Netzwerke.svg}} </WRAP> <callout> <WRAP> <imgcaption imageNo1 | examples for networks> </imgcaption> {{drawio>Beispiele Netzwerke.svg}} </WRAP>
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   * Combine transforms to reduce complex resistive networks to an **unloaded / loaded divider** and to size $R_{\rm L}$ for given performance goals (tie-in to Block 07 figures).   * Combine transforms to reduce complex resistive networks to an **unloaded / loaded divider** and to size $R_{\rm L}$ for given performance goals (tie-in to Block 07 figures).
 </callout> </callout>
 +
 +~~PAGEBREAK~~ ~~CLEARFIX~~
 +===== Preparation at Home =====
 +
 +And again: 
 +  * Please read through the following chapter.
 +  * Also here, there are some clips for more clarification under 'Embedded resources'. 
 +
 +For checking your understanding please do the following exercise:
 +  * 4.5.3
 +
  
 ===== 90-minute plan ===== ===== 90-minute plan =====
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 ===== Exercises ===== ===== Exercises =====
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-==== Quick checks ==== 
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-#@TaskTitle_HTML@##@Lvl_HTML@#~~#@ee1_taskctr#~~.1  Title of the first exercise   
-#@TaskText_HTML@#    
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-Here is a simple exercise ... 
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-#@ResultBegin_HTML~Exercise1~@# 
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-Here is the solution of the Exercise 1 
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-#@ResultEnd_HTML@# 
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-#@TaskTitle_HTML@##@Lvl_HTML@#~~#@ee1_taskctr#~~.2  Title of the 2nd exercise   
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-Here is another simple exercise ... 
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-#@ResultBegin_HTML~Exercise2~@# 
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-Here is the solution of the Exercise 2 
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-#@TaskEnd_HTML@#  
-#@ResultEnd_HTML@# 
  
 ==== Longer exercises ==== ==== Longer exercises ====