Differences

This shows you the differences between two versions of the page.

Link to this comparison view

Both sides previous revision Previous revision
Next revision		 Previous revision
electrical_engineering_and_electronics_1:block05 [2025/10/10 21:41] – [Learning objectives] mexleadminelectrical_engineering_and_electronics_1:block05 [2026/01/10 13:23] (current) – mexleadmin
Line 1: Line 1:
-====== Block 05 — Resistive networks ======+====== Block 05 — Resistive Networks ======
  
-===== Learning objectives =====+===== 5.0 Intro ===== 
 + 
 +==== 5.0.1 Learning Objectives ====
 <callout> <callout>
 After this 90-minute block, you can After this 90-minute block, you can
Line 10: Line 12:
 </callout> </callout>
  
-===== Preparation at Home =====+==== 5.0.2 Preparation at Home ====
  
 And again:  And again: 
Line 21: Line 23:
  
 ~~PAGEBREAK~~ ~~CLEARFIX~~ ~~PAGEBREAK~~ ~~CLEARFIX~~
-===== 90-minute plan  =====+==== 5.0.3 90-minute Plan  ====
   * 0–10 min — Recap KCL/KVL; sign conventions.   * 0–10 min — Recap KCL/KVL; sign conventions.
   * 10–30 min — Series & parallel; quick numeric checks.   * 10–30 min — Series & parallel; quick numeric checks.
Line 30: Line 32:
  
 ~~PAGEBREAK~~ ~~CLEARFIX~~ ~~PAGEBREAK~~ ~~CLEARFIX~~
-===== Core Content ===== +===== 5.1 Core Content ===== 
-==== Unloaded voltage divider ====+==== 5.1.1 Unloaded Voltage Divider ====
  
 The series circuit of two resistors $R_1$ and $R_2$ shall be considered now. \\ The series circuit of two resistors $R_1$ and $R_2$ shall be considered now. \\
Line 72: Line 74:
  
 ~~PAGEBREAK~~ ~~CLEARFIX~~ ~~PAGEBREAK~~ ~~CLEARFIX~~
-==== The loaded Voltage Divider ====+==== 5.1.2 The loaded Voltage Divider ====
  
 If - in contrast to the abovementioned, unloaded voltage divider - a load $R_{\rm L}$ is connected to the output terminals (<imgref BildNr15>), this load influences the output voltage. If - in contrast to the abovementioned, unloaded voltage divider - a load $R_{\rm L}$ is connected to the output terminals (<imgref BildNr15>), this load influences the output voltage.
Line 86: Line 88:
 $ U_1 = \LARGE{{U} \over {1 + {{R_2}\over{R_L}} + {{R_2}\over{R_1}} }}$ $ U_1 = \LARGE{{U} \over {1 + {{R_2}\over{R_L}} + {{R_2}\over{R_1}} }}$
  
-or on a potentiometer with $k$ and the sum of resistors $R_{\rm s} = R_1 + R_2$:+An alternative representation of the formula sticks more to the application. \\  
 +It uses: 
 +  - the position on a potentiometer given as $k={{R_1}\over{R_1 + R_2}}$ and  
 +  - the sum of resistors $R_{\rm s} = R_1 + R_2$. 
 +Both are more often used in real setups.
  
-$ U_1 = \LARGE{{k \cdot U} \over { 1 + k \cdot (1-k) \cdot{{R_{\rm s}}\over{R_{\rm L}}} }}$+Mathematically, both parameter lead to $R_1 = k \cdot R_{\rm s}$ and $R_2 = (1 - k) \cdot R_{\rm s}$. \\ 
 +When these tyo relations are included in rhe the formula above, we get:  
 + 
 +$ U_1 = U \cdot k \cdot \LARGE{{1} \over { 1 + k \cdot (1-k) \cdot{{R_{\rm s}}\over{R_{\rm L}}} }}$
  
 <imgref BildNr65> shows the ratio of the output voltage $U_1$ to the input voltage $U$ (y-axis), in relation to the ratio $k={{R_1}\over{R_1 + R_2}}$.  <imgref BildNr65> shows the ratio of the output voltage $U_1$ to the input voltage $U$ (y-axis), in relation to the ratio $k={{R_1}\over{R_1 + R_2}}$. 
Line 107: Line 116:
  
 ~~PAGEBREAK~~ ~~CLEARFIX~~ ~~PAGEBREAK~~ ~~CLEARFIX~~
-==== Bridge networks (Wheatstone) ====+==== 5.1.3 Bridge Networks (Wheatstone) ====
 A four-resistor bridge can be seen as **two voltage dividers in parallel**. The detector (bridge branch) sees the **difference** of the two divider node voltages. The **balance condition** (zero detector current) is A four-resistor bridge can be seen as **two voltage dividers in parallel**. The detector (bridge branch) sees the **difference** of the two divider node voltages. The **balance condition** (zero detector current) is
 \begin{align*} \begin{align*}
Line 119: Line 128:
  
 ~~PAGEBREAK~~ ~~CLEARFIX~~ ~~PAGEBREAK~~ ~~CLEARFIX~~
-==== Strategy for network reduction ====+==== 5.1.4 Strategy for network reduction ====
   * Reshape (without changing node connections), then collapse **clear** series or parallel groups.   * Reshape (without changing node connections), then collapse **clear** series or parallel groups.
-  * If blocked by a three-terminal cluster, apply **Δ–Y** (or **Y–Δ**), then collapse again.+  * (If blocked by a three-terminal cluster, apply **Δ–Y** (or **Y–Δ**), then collapse again. {{wp>Y-Δ_transform|Y–Δ and Δ–Y}} ist not covered and necessary in this course)
   * Repeat until a simple ladder remains; finish with KCL/KVL if needed.    * Repeat until a simple ladder remains; finish with KCL/KVL if needed. 
  
Line 159: Line 168:
      
 ~~PAGEBREAK~~ ~~CLEARFIX~~ ~~PAGEBREAK~~ ~~CLEARFIX~~
-===== Exercises =====+===== 5.2 Exercises =====
  
 <panel type="info" title="Exercise 2.4.3 Three Resistors"> <WRAP group><WRAP column 2%>{{fa>pencil?32}}</WRAP><WRAP column 92%> <panel type="info" title="Exercise 2.4.3 Three Resistors"> <WRAP group><WRAP column 2%>{{fa>pencil?32}}</WRAP><WRAP column 92%>
Line 299: Line 308:
  
  
-{{page>aufgabe_2.7.7_mit_rechnung&nofooter}} +{{page>electrical_engineering_and_electronics:aufgabe_2.7.7_mit_rechnung&nofooter}} 
-{{page>aufgabe_2.7.8_mit_rechnung&nofooter}} +{{page>electrical_engineering_and_electronics:aufgabe_2.7.8_mit_rechnung&nofooter}} 
-{{page>aufgabe_2.7.9&nofooter}} +{{page>electrical_engineering_and_electronics:aufgabe_2.7.9&nofooter}} 
-{{page>aufgabe_2.7.10&nofooter}}+{{page>electrical_engineering_and_electronics:aufgabe_2.7.10&nofooter}} 
 + 
 +{{page>electrical_engineering_and_electronics:task_cgeyprm6oboukcci_with_calculation&nofooter}} 
 +{{page>electrical_engineering_and_electronics:task_erlctd760zmvox0t_with_calculation&nofooter}} 
 +{{page>electrical_engineering_and_electronics:task_x357drkaqv84jnsc_with_calculation&nofooter}}