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electrical_engineering_and_electronics_1:block05 [2025/09/28 23:30] – angelegt mexleadminelectrical_engineering_and_electronics_1:block05 [2025/10/24 18:29] (aktuell) – [The loaded Voltage Divider] mexleadmin
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 ===== Learning objectives ===== ===== Learning objectives =====
 +<callout>
 After this 90-minute block, you can After this 90-minute block, you can
   * reduce series/parallel resistor networks to an equivalent resistance $R_{\rm eq}$,   * reduce series/parallel resistor networks to an equivalent resistance $R_{\rm eq}$,
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   * recognize and analyze **bridge** circuits (Wheatstone; balance condition),   * recognize and analyze **bridge** circuits (Wheatstone; balance condition),
   * check results by units and by “sanity bounds” (e.g., $R_{\rm eq}$ in parallel is below the smallest branch).   * check results by units and by “sanity bounds” (e.g., $R_{\rm eq}$ in parallel is below the smallest branch).
 +</callout>
 +
 +===== Preparation at Home =====
 +
 +And again: 
 +  * Please read through the following chapter.
 +  * Also here, there are some clips for more clarification under 'Embedded resources' (check the text above/below, sometimes only part of the clip is interesting). 
  
 +For checking your understanding please do the following exercises:
 +  * 2.5.3
 +  * 2.7.8
  
 ~~PAGEBREAK~~ ~~CLEARFIX~~ ~~PAGEBREAK~~ ~~CLEARFIX~~
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 ~~PAGEBREAK~~ ~~CLEARFIX~~ ~~PAGEBREAK~~ ~~CLEARFIX~~
 ===== Core Content ===== ===== Core Content =====
-==== Recap (from Block 04) ==== 
-Kirchhoff’s laws on **nodes** and **loops** plus reshaping circuits are the tools behind everything in this block. The node sign rule we use: arrows **toward** the node positive, **away** negative, $\sum I=0$.  
- 
-<panel type="info" title="Dimensional check"> 
-For the **current divider** relation $\displaystyle \frac{I_1}{I_2}=\frac{G_1}{G_2}$ both sides are ratios → dimensionless. Since $[G]=1~{\rm S}$, the unit cancels. (We will re-derive it below.)  
-</panel> 
- 
-~~PAGEBREAK~~ ~~CLEARFIX~~ 
- 
 ==== Unloaded voltage divider ==== ==== Unloaded voltage divider ====
  
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 ~~PAGEBREAK~~ ~~CLEARFIX~~ ~~PAGEBREAK~~ ~~CLEARFIX~~
-<panel type="info" title="Exercise 2.5.1 unloaded voltage divider"> <WRAP group><WRAP column 2%>{{fa>pencil?32}}</WRAP><WRAP column 92%>+<panel type="info" title="Exercise"> <WRAP group><WRAP column 2%>{{fa>pencil?32}}</WRAP><WRAP column 92%>
  
 <WRAP> <WRAP>
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 $ U_1 = \LARGE{{U} \over {1 + {{R_2}\over{R_L}} + {{R_2}\over{R_1}} }}$ $ U_1 = \LARGE{{U} \over {1 + {{R_2}\over{R_L}} + {{R_2}\over{R_1}} }}$
  
-or on a potentiometer with $k$ and the sum of resistors $R_{\rm s} = R_1 + R_2$:+An alternative representation of the formula sticks more to the application. \\  
 +It uses: 
 +  - the position on a potentiometer given as $k={{R_1}\over{R_1 + R_2}}$ and  
 +  - the sum of resistors $R_{\rm s} = R_1 + R_2$. 
 +Both are more often used in real setups. 
 + 
 +Mathematically, both parameter lead to $R_1 = k \cdot R_{\rm s}$ and $R_2 = (1 - k) \cdot R_{\rm s}$. \\ 
 +When these tyo relations are included in rhe the formula above, we get: 
  
-$ U_1 = \LARGE{{k \cdot U} \over { 1 + k \cdot (1-k) \cdot{{R_{\rm s}}\over{R_{\rm L}}} }}$+$ U_1 = U \cdot k \cdot \LARGE{{1} \over { 1 + k \cdot (1-k) \cdot{{R_{\rm s}}\over{R_{\rm L}}} }}$
  
 <imgref BildNr65> shows the ratio of the output voltage $U_1$ to the input voltage $U$ (y-axis), in relation to the ratio $k={{R_1}\over{R_1 + R_2}}$.  <imgref BildNr65> shows the ratio of the output voltage $U_1$ to the input voltage $U$ (y-axis), in relation to the ratio $k={{R_1}\over{R_1 + R_2}}$. 
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 ==== Strategy for network reduction ==== ==== Strategy for network reduction ====
   * Reshape (without changing node connections), then collapse **clear** series or parallel groups.   * Reshape (without changing node connections), then collapse **clear** series or parallel groups.
-  * If blocked by a three-terminal cluster, apply **Δ–Y** (or **Y–Δ**), then collapse again.+  * (If blocked by a three-terminal cluster, apply **Δ–Y** (or **Y–Δ**), then collapse again. {{wp>Y-Δ_transform|Y–Δ and Δ–Y}} ist not covered and necessary in this course)
   * Repeat until a simple ladder remains; finish with KCL/KVL if needed.    * Repeat until a simple ladder remains; finish with KCL/KVL if needed. 
  
-In this subchapter, a methodology is discussed, which should help to reshape circuits. In subchapter [[#2.6 Star-Delta-Circuit]] towards the end a network was already transformed in a way, that it does not contain triangular meshes anymore. Now, this procedure shall be systematized. +In this subchapter, a methodology is discussed, which should help to reshape circuits.  
-Starting points are tasks, where for a resistor network the total resistance, total current, or total voltage has to be calculated.+The following concept works at tasks, where the total resistance, total current, or total voltage has to be calculated for a resistor network.
  
 An example of such a circuit is given in <imgref imageNo89>. Here $I_0$ is wanted.  An example of such a circuit is given in <imgref imageNo89>. Here $I_0$ is wanted.