| Beide Seiten der vorigen Revision Vorhergehende Überarbeitung Nächste Überarbeitung | Vorhergehende Überarbeitung |
| circuit_design:2_transistors [2023/03/28 08:45] – mexleadmin | circuit_design:2_transistors [2023/11/30 01:11] (aktuell) – mexleadmin |
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| ====== 2. Diodes and Transistors ====== | ====== 2 Diodes and Transistors ====== |
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| <WRAP> | <WRAP> |
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| - Figure: The physics of this takes place in the narrow P-layer. The following images refer to the highlighted section. | - Figure: The physics of this takes place in the narrow P-layer. The following images refer to the highlighted section. |
| - Figure - Situation $U_{\rm CE}=0~{\rm V}, U_{\rm BE}=0\rm V$: In this picture the unpowered transistor is shown. In it the free charge carriers (electrons in green, holes in red) and the junction layers between base and emitter, and base and collector in yellow. Only the junction layer shows the stationary charge carriers with their sign. As shown in the band model, the stationary charge carriers are present everywhere in both doped regions. | - Figure - Situation $U_{\rm CE}=0~{\rm V}, U_{\rm BE}=0 ~\rm V$: In this picture the unpowered transistor is shown. In it the free charge carriers (electrons in green, holes in red) and the junction layers between base and emitter, and base and collector in yellow. Only the junction layer shows the stationary charge carriers with their sign. As shown in the band model, the stationary charge carriers are present everywhere in both doped regions. |
| - Figure - Situation $U_{\rm CE}=0~{\rm V}, 0~{\rm V}<U_{\rm BE}<0.6~\rm V$: First, consider a small, positive voltage $U_{\rm BE}$. This provides holes in the base with current $I_\rm B$. This operates the PN junction between the base and emitter in the forward direction. In the figure, it is indicated with black circles that the injected holes compensate some stationary negative charge carriers in both junction layers. Electrons also flow through the emitter into the n-region, which attenuates the junction on the other side. | - Figure - Situation $U_{\rm CE}=0~{\rm V}, 0~{\rm V}<U_{\rm BE}<0.6~\rm V$: First, consider a small, positive voltage $U_{\rm BE}$. This provides holes in the base with current $I_\rm B$. This operates the PN junction between the base and emitter in the forward direction. In the figure, it is indicated with black circles that the injected holes compensate some stationary negative charge carriers in both junction layers. Electrons also flow through the emitter into the n-region, which attenuates the junction on the other side. |
| - Figure - Situation $U_{\rm CE}=0~{\rm V}, U_{\rm BE}>0.6 \rm V$: When the forward voltage of the PN junction between the base and emitter is exceeded, the injected holes and electrons cancel the bottom junction. In the simulation below, it can be seen that the circuitry of the transistor is such that in the diode circuit (which is not physically correct), the diode between the base and emitter becomes conductive. | - Figure - Situation $U_{\rm CE}=0~{\rm V}, U_{\rm BE}>0.6 \rm V$: When the forward voltage of the PN junction between the base and emitter is exceeded, the injected holes and electrons cancel the bottom junction. In the simulation below, it can be seen that the circuitry of the transistor is such that in the diode circuit (which is not physically correct), the diode between the base and emitter becomes conductive. |
| In the previous chapter [[1 Amplifier basics]] the characteristics of a black box have already been discussed, there, especially for an amplifier. The methodology can also be applied here. In the video above, the first parameter has already been described: The **current gain** $\beta=\frac{I_\rm C}{I_\rm B}$, or in the form of a graph, the **current gain characteristic** $I_{\rm C}(I_\rm B)$.[(Note1>In practice, a distinction is still made between small-signal current gain $\beta = h_{\rm fe} = \frac{{\rm d} I_{\rm C}}{{\rm d} I_{\rm B}}$ and large-signal current gain $B = h_{\rm FE}= \frac{I_{\rm C}}{I_{\rm B}}$. In small-signal behavior, a relatively small change around a fixed operating point (e.g., around certain values $I_\rm C$ and $U_{\rm CE}$) is considered. In large-signal behavior, a change between 0 and a given value is considered. For nonlinear characteristics, the two quantities may differ. In this course, only the small-signal behavior is described. The large-signal behavior and the distinction between the two considerations are not considered in this course)]. | In the previous chapter [[1 Amplifier basics]] the characteristics of a black box have already been discussed, there, especially for an amplifier. The methodology can also be applied here. In the video above, the first parameter has already been described: The **current gain** $\beta=\frac{I_\rm C}{I_\rm B}$, or in the form of a graph, the **current gain characteristic** $I_{\rm C}(I_\rm B)$.[(Note1>In practice, a distinction is still made between small-signal current gain $\beta = h_{\rm fe} = \frac{{\rm d} I_{\rm C}}{{\rm d} I_{\rm B}}$ and large-signal current gain $B = h_{\rm FE}= \frac{I_{\rm C}}{I_{\rm B}}$. In small-signal behavior, a relatively small change around a fixed operating point (e.g., around certain values $I_\rm C$ and $U_{\rm CE}$) is considered. In large-signal behavior, a change between 0 and a given value is considered. For nonlinear characteristics, the two quantities may differ. In this course, only the small-signal behavior is described. The large-signal behavior and the distinction between the two considerations are not considered in this course)]. |
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| Another characteristic is the **input characteristic** $U_{\rm BE}({I_\rm B})$ or as differential characteristic (=slope in the characteristic) the **differential input resistance** $r_{\rm BE}=\frac{{\rm d} U_{rm BE}}{{\rm d} I_\rm B}$. As described earlier, the structure between the base and emitter resembles a diode. Accordingly, the input characteristic resembles that of a diode. Since the current flow $I_\rm B$ is very small (a few microamps or smaller), the input resistance $r_{\rm BE}$ is large. | Another characteristic is the **input characteristic** $U_{\rm BE}({I_\rm B})$ or as differential characteristic (=slope in the characteristic) the **differential input resistance** $r_{\rm BE}=\frac{{\rm d} U_{\rm BE}}{{\rm d} I_\rm B}$. As described earlier, the structure between the base and emitter resembles a diode. Accordingly, the input characteristic resembles that of a diode. Since the current flow $I_\rm B$ is very small (a few microamps or smaller), the input resistance $r_{\rm BE}$ is large. |
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| The following simulation shows the current gain characteristic $I_{\rm C}(I_{\rm B})$ and input characteristic $U_{\rm BE}({I_\rm B})$ by varying $U_{\rm BE}$ (or $I_\rm B$). | The following simulation shows the current gain characteristic $I_{\rm C}(I_{\rm B})$ and input characteristic $U_{\rm BE}({I_\rm B})$ by varying $U_{\rm BE}$ (or $I_\rm B$). |
| ==== 2.7.2 Metal Oxide Semiconductor Field-Effect Transistor (MOSFET) ==== | ==== 2.7.2 Metal Oxide Semiconductor Field-Effect Transistor (MOSFET) ==== |
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| The structure of the metal oxide semiconductor field-effect transistor (**Metal Oxide Semiconductor Field-Effect Transistor: MOSFET)** resembles the bipolar junction transistor at first glance. In <imgref pic3>, the individual figures (1)...(3) show the layering of an n-channel (German: n-Kanal) MOSFET, and in (4) the circuit symbol is shown again. In contrast to the NPN-bipolar junction transistor, the middle P-doped layer (bulk) is not directly connected to the control electrode. Rather, the metal layer of the gate (<imgref pic3>, Fig. (5), gray), the insulating layer of the oxide (shown in purple), and the conductive P-doped layer of the bulk (shown in red) form a capacitor. It should be noted that the bulk is at the potential of the source connection (dotted line in the picture). | The structure of the metal oxide semiconductor field-effect transistor (**Metal Oxide Semiconductor Field-Effect Transistor: MOSFET)** resembles the bipolar junction transistor at first glance. In <imgref pic3>, the individual figures (1)...(3) show the layering of an N-channel (German: //N-Kanal//) MOSFET, and in (4) the circuit symbol is shown again. In contrast to the NPN-bipolar junction transistor, the middle P-doped layer (bulk) is not directly connected to the control electrode. Rather, the metal layer of the gate (<imgref pic3>, Fig. (5), gray), the insulating layer of the oxide (shown in purple), and the conductive P-doped layer of the bulk (shown in red) form a capacitor. It should be noted that the bulk is at the potential of the source connection (dotted line in the picture). |
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| <WRAP ><panel type="default"> | <WRAP ><panel type="default"> |
| Without voltage difference, $U_{\rm GS}$ between gate and source, a (small) junction is formed at the PN junctions. If the voltage difference $U_{\rm GS}$ is increased, the capacitor between the gate and bulk is charged. This accumulates electrons opposite the gate electrode (<imgref pic3>, Fig. (2), green "wedge"). If the voltage difference $U_{\rm GS}$ exceeds a certain threshold voltage, the enriched electrons form a channel between the source and the gate. This allows a current $I_\rm D \gg 0$ to flow through the MOSFET (<imgref pic3> Fig. (3)). | Without voltage difference, $U_{\rm GS}$ between gate and source, a (small) junction is formed at the PN junctions. If the voltage difference $U_{\rm GS}$ is increased, the capacitor between the gate and bulk is charged. This accumulates electrons opposite the gate electrode (<imgref pic3>, Fig. (2), green "wedge"). If the voltage difference $U_{\rm GS}$ exceeds a certain threshold voltage, the enriched electrons form a channel between the source and the gate. This allows a current $I_\rm D \gg 0$ to flow through the MOSFET (<imgref pic3> Fig. (3)). |
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| The switching symbol (<imgref pic3>, figure (4)) can also be described as follows: Capacitors form between gate and source, between gate and base, and between gate and drain, respectively, in the off state because of the oxide layer (purple in Fig. (1))[(Note2>In field-effect transistors, an additional capacitor forms between source and drain, which can lead to overvoltages at the MOSFET, especially during fast switching of inductors)]. To drive the MOSFET, the voltage at the gate $U_{\rm GS}$ must be such that a PN junction forms in the bulk, indicated by the white-filled triangle in figure (4). Since the apex of the triangle (or the diode symbol sketched with it) points toward the gate, it is clear that we are dealing with an n-channel MOSFET. | The switching symbol (<imgref pic3>, figure (4)) can also be described as follows: Capacitors form between gate and source, between gate and base, and between gate and drain, respectively, in the off state because of the oxide layer (purple in Fig. (1))[(Note2>In field-effect transistors, an additional capacitor forms between source and drain, which can lead to overvoltages at the MOSFET, especially during fast switching of inductors)]. To drive the MOSFET, the voltage at the gate $U_{\rm GS}$ must be such that a PN junction forms in the bulk, indicated by the white-filled triangle in figure (4). Since the apex of the triangle (or the diode symbol sketched with it) points toward the gate, it is clear that we are dealing with an N-channel MOSFET. |
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| ==== 2.7.4 Variants of MOSFETs ==== | ==== 2.7.4 Variants of MOSFETs ==== |
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| The so far considered (and also most frequently used) field-effect transistor is the so-called "**n-channel enhancement type MOSFET**". The part "n-channel" comes from the type of the current-forming charge carrier and was already given above. The part "enhancement type" represents, that the charge carriers are not present at first and have to be accumulated in the bulk using the voltage $U_{\rm GS}$ for conductivity. | The so far considered (and also most frequently used) field-effect transistor is the so-called "**N-channel enhancement type MOSFET**". The part "N-channel" comes from the type of the current-forming charge carrier and was already given above. The part "enhancement type" represents, that the charge carriers are not present at first and have to be accumulated in the bulk using the voltage $U_{\rm GS}$ for conductivity. |
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| Some circuits (especially digital circuits) also use "**p-channel enhancement type MOSFET**", where holes are the current-forming charge carriers. In the simulation, this type of MOSFET is shown. Most clearly, when the p-channel enhancement type MOSFET is connected, the drain and source are generally reversed. Thus, the numerical values of $U_{\rm DS}$ and $I_\rm D$ in the output characteristics become negative. To enrich holes in the p-channel, a negative voltage must be applied to the gate $U_{\rm DS}<0$. | Some circuits (especially digital circuits) also use "**P-channel enhancement type MOSFET**", where holes are the current-forming charge carriers. In the simulation, this type of MOSFET is shown. Most clearly, when the P-channel enhancement type MOSFET is connected, the drain and source are generally reversed. Thus, the numerical values of $U_{\rm DS}$ and $I_\rm D$ in the output characteristics become negative. To enrich holes in the P-channel, a negative voltage must be applied to the gate $U_{\rm DS}<0$. |
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| In the <imgref pic2> the circuit symbols of different variants of MOSFETs are shown. In the MOSFETs in the top row, an n-channel is formed for charge transport, and in the bottom row, a p-channel is formed. | In the <imgref pic2> the circuit symbols of different variants of MOSFETs are shown. In the MOSFETs in the top row, an N-channel is formed for charge transport, and in the bottom row, a P-channel is formed. |
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| Three variations of an **n-channel enhancement type MOSFET** are shown in <imgref pic2> in the upper left. In the first circuit symbol, the circle represents that it is a discrete device, i.e., a single MOSFET not integrated with others in a chip. The second circuit symbol has already been used in the previous chapters. The third circuit symbol of the same n-channel enhancement type MOSFET is the reduced version (i.e., without bulk). This representation is used for simplification in digital circuits. | Three variations of an **N-channel enhancement type MOSFET** are shown in <imgref pic2> in the upper left. In the first circuit symbol, the circle represents that it is a discrete device, i.e., a single MOSFET not integrated with others in a chip. The second circuit symbol has already been used in the previous chapters. The third circuit symbol of the same N-channel enhancement type MOSFET is the reduced version (i.e., without bulk). This representation is used for simplification in digital circuits. |
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| In <imgref pic2> on the lower left, three variations of a **p-channel enhancement type MOSFET** are shown. Again, the circle on the first circuit symbol indicates that it is a discrete device, but now the direction of the arrow on the bulk is rotated. The second switching symbol is used in the same way as for the n-channel MOSFET - in integrated circuits. The third symbol is again the reduced version (without bulk). For the digital circuit, it is only important whether the switch closes or opens at a high signal ($= 5~\rm V$). Since the p-channel enhancement type MOSFET opens, this is drawn with a negation sign (small circle) at the gate. | In <imgref pic2> on the lower left, three variations of a **P-channel enhancement type MOSFET** are shown. Again, the circle on the first circuit symbol indicates that it is a discrete device, but now the direction of the arrow on the bulk is rotated. The second switching symbol is used in the same way as for the N-channel MOSFET - in integrated circuits. The third symbol is again the reduced version (without bulk). For the digital circuit, it is only important whether the switch closes or opens at a high signal ($= 5~\rm V$). Since the P-channel enhancement type MOSFET opens, this is drawn with a negation sign (small circle) at the gate. |
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| ~~PAGEBREAK~~ ~~CLEARFIX~~ | ~~PAGEBREAK~~ ~~CLEARFIX~~ |
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| In <imgref pic2> on the right, the so-called **n-channel and p-channel depletion-type MOSFET** are shown. The MOSFETs considered so far were not conductive in the off state (i.e. $U_{\rm DS}=0$). However, in some applications, it would be good if the MOSFET resembled a conductive switch when off. Looking at the layer structure (<imgref pic3>, Figure (1)...(3)), this is possible via selective re-doping of the region opposite the gate. The doping can be used to dislocate a conductive channel. The charge carriers of this channel can be displaced or depleted by a suitable electric field - and thus suitable gate voltage $U_{\rm GS}$. Thus, the MOSFET becomes non-conducting in the presence of a reverse voltage $U_{\rm GS}$. In the circuit symbol, the "short circuit" between the source and drain is also drawn pictorially. | In <imgref pic2> on the right, the so-called **N-channel and P-channel depletion-type MOSFET** are shown. The MOSFETs considered so far were not conductive in the off state (i.e. $U_{\rm DS}=0$). However, in some applications, it would be good if the MOSFET resembled a conductive switch when off. Looking at the layer structure (<imgref pic3>, Figure (1)...(3)), this is possible via selective re-doping of the region opposite the gate. The doping can be used to dislocate a conductive channel. The charge carriers of this channel can be displaced or depleted by a suitable electric field - and thus suitable gate voltage $U_{\rm GS}$. Thus, the MOSFET becomes non-conducting in the presence of a reverse voltage $U_{\rm GS}$. In the circuit symbol, the "short circuit" between the source and drain is also drawn pictorially. |
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| <WRAP group> | <WRAP group> |
| There are 4 different types of MOSFETs. | There are 4 different types of MOSFETs. |
| On the one hand, these differ in the type of current-forming charge carriers: | On the one hand, these differ in the type of current-forming charge carriers: |
| * **n-channel**: The current-forming charge carriers are electrons. | * **N-channel**: The current-forming charge carriers are electrons. |
| * **p-channel**: The current-forming charge carriers are holes. | * **P-channel**: The current-forming charge carriers are holes. |
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| The second distinguishing feature is the off-state conductivity ($U_{\rm GS}=0$): | The second distinguishing feature is the off-state conductivity ($U_{\rm GS}=0$): |
| Due to the heating of the component and the resulting increase in intrinsic conduction, two limit values result: | Due to the heating of the component and the resulting increase in intrinsic conduction, two limit values result: |
| * In the conducting state, the power dissipation $P_{\rm loss}=R(T)\cdot I^2$ forms a direct reference to the current through the semiconductor element $I_{\rm C}, I_{\rm D}, I_{\rm D}$ (bipolar junction transistor, MOSFET, diode). This results in current $I_{\rm max}$, which should not be exceeded. | * In the conducting state, the power dissipation $P_{\rm loss}=R(T)\cdot I^2$ forms a direct reference to the current through the semiconductor element $I_{\rm C}, I_{\rm D}, I_{\rm D}$ (bipolar junction transistor, MOSFET, diode). This results in current $I_{\rm max}$, which should not be exceeded. |
| * In the state where there is both a noticeable current and voltage, there is a maximum allowed power $P_{\rm tot}=const.=U\cdot I$. This is a hyperbola in the output characteristic. If the output current exceeds this hyperbola, the semiconductor element heats up to such an extent that, due to the increasing intrinsic conductivity, the conductivity drops, which in turn leads to an increasing current. This effect leads to the thermal destruction of the component. | * In the state where there is both a noticeable current and voltage, there is a maximum allowed power $P_{\rm tot}={\rm const.}=U\cdot I$. This is a hyperbola in the output characteristic. If the output current exceeds this hyperbola, the semiconductor element heats up to such an extent that, due to the increasing intrinsic conductivity, the conductivity drops, which in turn leads to an increasing current. This effect leads to the thermal destruction of the component. |
| In addition, a maximum voltage $U_{\rm max}$ must not be exceeded. This is usually due to the (internal) dielectric strength of the component. | In addition, a maximum voltage $U_{\rm max}$ must not be exceeded. This is usually due to the (internal) dielectric strength of the component. |
| |
| |
| During electronics development, several integrated circuits (e.g. intelligent light sensor, microcontroller, intelligent LED) may require different voltage levels. This can lead to problems especially during data exchange if logic High has to be in a certain voltage range. This problem can be solved by a level converter. | During electronics development, several integrated circuits (e.g. intelligent light sensor, microcontroller, intelligent LED) may require different voltage levels. This can lead to problems especially during data exchange if logic High has to be in a certain voltage range. This problem can be solved by a level converter. |
| The level converter (also logic level converter, level shifter) enables the bidirectional connection of digital connections of different voltage levels, e.g. 5 V to 3.3 V. | The level converter (also logic level converter, level shifter) enables the bidirectional connection of digital connections of different voltage levels, e.g. $5 ~\rm V$ to $3.3 ~\rm V$. |
| |
| <WRAP>{{url>https://www.falstad.com/circuit/circuitjs.html?running=false&ctz=CQAgjCAMB0l3BWK0wCYDMYBsGsBYM8B2SPATiJCIiQUgCgAzEdUkVVPFt1BLF1OGhIYkVPXRdGAdwAmAJwD2ABwA6ARxgAOSP0hDqaOGDJgieBJLDoApgFpK+wQ1nstWtx-Son7liBkFFQ1tXXppASc+SM8ocNjeflQ-ZI8GCNT2aI4uRLiMziz+MyTo9Ji89C1csviqmv48fCK4+RZqlvrwIj1weDh6NpyW4ZKoPv76ACV2QrHRvC59fTx9dGh0ceXhafauMa6wRa2QVZARLZ2C-Z7uG706tgOeQoYAGRBmnzT2SB+IRgAQwANgBnGwsDZxACy51ueXwUV66yIEiwHmGeUxRGccXQ6L2nQ6qBxW3osK+ZRaTh2AEkQGR+N59IzYttaPFWSZBHgPNz8qc+WQeV58QLeSwxaz0GLytKpUyfALWZkVaTymgMdF5rUIprfnzktT6B8JTLkbLxkCwRD1pt3udjubPmdnfoASDwZD7fEmrk-qdKQ8IghjplQ7l1fEI5L+DHmeL5XGnbLfVzhackwKY-zyMUMwx6fGlTHMuzzr6vgGEGgDeKg+da3kHQh4QHEXX3QFPRCRPQwAgyOAjd8XZ3fhN+pMB0OG-rmxOwFOp-3B43BHlW6Vekql8v4Kuh1u6zWNwGnO79weAB4gByCdAIPkmFhYCD7DwAEQAlvIbABjAAXb9FAAO1UUEACFv0AiCAAoAAkNAAeQAV0A5R0IASnoW9eS8NcsCIId8R5cAv1-ADgLAiDoNg0FEJQ9DMMAnDbwcJxvD6dhH1OciQDQjD0NomDcLvUkSUoOwkh0PiwA8WlQJYkTALEt8kEkz4tAgZIVn4xTlKg0Tb0HIcOA8IizMwOSPEEwy6PoAAjU4JQHCASHfF8GHY0MXOKPBNkWIcPxAaFv3-JR-zAwClGBYEbHkeCaNBO0ADU2NOSwXMoLA6EyvT5NC8LIui2L4sShjkoQWB0qc8ShwHd1zFOQqGCAA noborder}} | <WRAP>{{url>https://www.falstad.com/circuit/circuitjs.html?running=false&ctz=CQAgjCAMB0l3BWK0wCYDMYBsGsBYM8B2SPATiJCIiQUgCgAzEdUkVVPFt1BLF1OGhIYkVPXRdGAdwAmAJwD2ABwA6ARxgAOSP0hDqaOGDJgieBJLDoApgFpK+wQ1nstWtx-Son7liBkFFQ1tXXppASc+SM8ocNjeflQ-ZI8GCNT2aI4uRLiMziz+MyTo9Ji89C1csviqmv48fCK4+RZqlvrwIj1weDh6NpyW4ZKoPv76ACV2QrHRvC59fTx9dGh0ceXhafauMa6wRa2QVZARLZ2C-Z7uG706tgOeQoYAGRBmnzT2SB+IRgAQwANgBnGwsDZxACy51ueXwUV66yIEiwHmGeUxRGccXQ6L2nQ6qBxW3osK+ZRaTh2AEkQGR+N59IzYttaPFWSZBHgPNz8qc+WQeV58QLeSwxaz0GLytKpUyfALWZkVaTymgMdF5rUIprfnzktT6B8JTLkbLxkCwRD1pt3udjubPmdnfoASDwZD7fEmrk-qdKQ8IghjplQ7l1fEI5L+DHmeL5XGnbLfVzhackwKY-zyMUMwx6fGlTHMuzzr6vgGEGgDeKg+da3kHQh4QHEXX3QFPRCRPQwAgyOAjd8XZ3fhN+pMB0OG-rmxOwFOp-3B43BHlW6Vekql8v4Kuh1u6zWNwGnO79weAB4gByCdAIPkmFhYCD7DwAEQAlvIbABjAAXb9FAAO1UUEACFv0AiCAAoAAkNAAeQAV0A5R0IASnoW9eS8NcsCIId8R5cAv1-ADgLAiDoNg0FEJQ9DMMAnDbwcJxvD6dhH1OciQDQjD0NomDcLvUkSUoOwkh0PiwA8WlQJYkTALEt8kEkz4tAgZIVn4xTlKg0Tb0HIcOA8IizMwOSPEEwy6PoAAjU4JQHCASHfF8GHY0MXOKPBNkWIcPxAaFv3-JR-zAwClGBYEbHkeCaNBO0ADU2NOSwXMoLA6EyvT5NC8LIui2L4sShjkoQWB0qc8ShwHd1zFOQqGCAA noborder}} |
| </WRAP> | </WRAP> |
| |
| For the level converter, any n-channel enhancement MOSFET whose threshold voltage is below $1.8...2.0 ~\rm V$ can be used. This limit is due to the minimum logic level of $2.0 ~\rm V$ for logic high. For simplicity, "logic level enhancement mode MOSFET" is used, which is just optimized for the logic voltage of $3.3 ~\rm V$. | For the level converter, any N-channel enhancement MOSFET whose threshold voltage is below $1.8...2.0 ~\rm V$ can be used. This limit is due to the minimum logic level of $2.0 ~\rm V$ for logic high. For simplicity, "logic level enhancement mode MOSFET" is used, which is just optimized for the logic voltage of $3.3 ~\rm V$. |
| |
| The way it works is well explained on [[https://en.wikipedia.org/wiki/Level_shifter|Wikipedia]] and can be derived with simulation. | The way it works is well explained on [[https://en.wikipedia.org/wiki/Level_shifter|Wikipedia]] and can be derived with simulation. |
| ==== 2.9.4 Voltage Doubler/Inverter ==== | ==== 2.9.4 Voltage Doubler/Inverter ==== |
| |
| As a power supply for electronics, $5 ~\rm V$ or $3.3 ~\rm V$ is often used. In the following chapter, we will see that a bipolar power supply is often used for operational amplifier circuits. To be able to generate $-5 ~\rm V$ at low currents from a $5 ~\rm V$ supply, [[https://en.wikipedia.org/wiki/Charge_pump|charge pumps]] are often used. One such can be seen in the simulation. In the oscilloscope (in the simulation below), the voltage $U_{\rm C1}$ is displayed at the input capacitor C1 and $U_{\rm C2}$ at the storage capacitor C1. This circuit can be found, for example, in IC [[https://www.renesas.com/eu/en/www/doc/datasheet/icl7660.pdf|ICL7660]] (Renesas), [[https://www.ti.com/lit/ds/symlink/lmc7660.pdf|LMC7660]] (TI), [[http://ww1.microchip.com/downloads/en/DeviceDoc/21465C.pdf|TC7660]] (Microchip) integrated. Details on how it works can be found in [[https://www.youtube.com/watch?v=LYKGuc6ibe0&ab_channel=tanzawalab|this video]], for example. | As a power supply for electronics, $5 ~\rm V$ or $3.3 ~\rm V$ is often used. In the following chapter, we will see that a bipolar power supply is often used for operational amplifier circuits. To be able to generate $-5 ~\rm V$ at low currents from a $5 ~\rm V$ supply, [[https://en.wikipedia.org/wiki/Charge_pump|charge pumps]] are often used. One such can be seen in the simulation. In the oscilloscope (in the simulation below), the voltage $U_{\rm C1}$ is displayed at the input capacitor $C1$ and $U_{\rm C2}$ at the storage capacitor C1. This circuit can be found, for example, in IC [[https://www.renesas.com/eu/en/www/doc/datasheet/icl7660.pdf|ICL7660]] (Renesas), [[https://www.ti.com/lit/ds/symlink/lmc7660.pdf|LMC7660]] (TI), [[http://ww1.microchip.com/downloads/en/DeviceDoc/21465C.pdf|TC7660]] (Microchip) integrated. Details on how it works can be found in [[https://www.youtube.com/watch?v=LYKGuc6ibe0&ab_channel=tanzawalab|this video]], for example. |
| |
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| Study Questions: | Study Questions: |
| |
| * In which state is the voltage $U_{\rm C1}$ equal to $1 ~\rm V$? * In which state is the difference between the voltages $U_{\rm C2}-U_{\rm C1}$ across the two capacitors equal to $1 ~\rm V$? | * In which state is the voltage $U_{\rm C1}$ equal to $1 ~\rm V$? |
| | * In which state is the difference between the voltages $U_{\rm C2}-U_{\rm C1}$ across the two capacitors equal to $1 ~\rm V$? |
| * What happens if the voltage sources for $0 ~\rm V$ and $1 ~\rm V$ are reversed? | * What happens if the voltage sources for $0 ~\rm V$ and $1 ~\rm V$ are reversed? |
| * How can this circuit be implemented with diodes instead of changeover switches? | * How can this circuit be implemented with diodes instead of changeover switches? |
| </WRAP> | </WRAP> |
| |
| ==== 2.9.7 Other MOSFET Applications==== | ==== 2.9.7 MOSFET as Substitution for Diodes ==== |
| | |
| | Diodes always show a voltage drop given by the forward voltage. To circumvent this issue a MOSFET can be used. \\ |
| | The following example shows one way to cope with it, when two voltage sources should be combined (e.g. a rechargeable battery with $U_1$ and a nonrechargable buffer battery with $U_2$): |
| | * The __left side__ depicts a way to combine the two voltages with diodes. The higher voltages will be led through the diode. The diode of the lower voltage is set in reverse, since the cathode of the diode is on the higher voltage \\ The disadvantages of this setup are: |
| | * One cannot choose the voltage on the output. It will be always given by the highest voltage. |
| | * There will always be the voltage drop of the diode |
| | * The __right side__ shows an alternative way to connect both voltages: the antiparallel p-MOSFETs avoid conductivity via the due to the body diode. The MOSFET pair is driven by a BJT in order to have a digital signal as an input. \\ The disadvantages of this setup are: |
| | * It is possible to short-circuit both voltages |
| | * It is more complex |
| | Often the rightside one can be simplified and the disadvantages can be avoided by using integrated circuits (like [[https://www.analog.com/en/products/ltc4417.html|LTC4417]]) |
| | |
| | |
| | <WRAP>{{url>https://www.falstad.com/circuit/circuitjs.html?ctz=CQAgzCAMB0l3AWAnC1b0DYQEYYCY48B2IsSADjwxSJAFZIdGEI6BTAWm2wCgAzcHhx5ygkAlFgI2aHSjQ8-EEizYRyrBPHYcs+YoDuYtaJXDRkHka1byzC1Zxrxo7BntRHbj3jwIXngBOIL7+WqE4CP6MuHA8AOYhfpH+EdhEWIyWwRzJ5KK5-iZQTHFGXGCaBWo+PAAuIBxa2FGNyS3ROPJ0GEShYETYSNhgQ0jyGHR0blQ92JTuzrEgACZsfACGAK4ANnUJbUXuhzgZJZZGYELFheZBjWYdjc2tMfCWADIPqq1c6k8xECbHYAZzY9E8Rm8AWhEQuOGOaWccJ4ACVnnZwOR-BxpkIwNjzuJGHIst00RjGGA6EJcc5qUIyQg3kSYHQeCtGnQzlpcepwqt1ts9hyuWcInzRBEhGtNrt9uUaVLkpKAvCIuF8mqeAAHEJazWuVoQLIHERG1Ja9KZTyJJpwFLPB3W866p0ee0xY2u8oIDBhArMjyWO1+oq-MOnG3ZZ7+gJNOMA0rw1W8yNaSwEWhNTEM55aPP+ACqvCzlKxOKikkJxcUZY4GGSvMmVXEIBLPHrjdSKpbSTC7brkGzIywEvmPYHRaHI8q8ZdNnbpeHJy1tzjxbUABoALYbAAenZXtyoOOSfmYS7wu4PPC+HDMV0Yf0kBCJwLBEJjD6wT4xgjJWIyjEMgz38UDbROKQsFuPNTQaHMAKgt9AQfaAWDoOxBl6XoaVIZRZGpLC3DIMBkDwdgOFcB1ZWFBVGlHfsGLfaUeByc841gyBOiAxxwjyRgUUufFuI0cBRMsARH1EswNR0GRSQUJQrnE8ChAiKRdEUmcQKQIQ4zAPS2xLa890Pes3HEFUbCbQcjxHX8jMQwyhE3RwVIQZIVJczxOS4TQvNc89BTlEU-MsnzvKMmUhXlHgACNnlknErnGXxGR4fcMSlBBswwkIGDbZIPgAew2FZMpCbgQmQEI4wo1yapAUryoSkJIAgKhwCIQTkhTbt43cURwkcBtz17CgmMMZiPEsjNRpqJjLJRRKG0gdScQYWgKOiNquGqrqhlc+byiGpjcXFPrRrO3luVbSwsrWy1n2QCBRkvZIAAUSoMNhAgAHX+gA7AAiAB5VEQf+kEAHENjqNhKofYaiCOMISCK-wAGUDAASzqABjAALDZ4p2Nhoe+36AZBABJIGdS2OoQR4AkcFEAAxHQyTfLgl1Z1xaC5oleZ0acBZCcZhbeGXnx0FqVmh1E2BBXGQTqErAglrBpfoWWQhAf7LCAA noborder}} |
| | </WRAP> |
| | |
| | |
| | ==== 2.9.8 Other MOSFET Applications==== |
| |
| MOSFETs are not only used for pure switching of currents. Further applications are also: | MOSFETs are not only used for pure switching of currents. Further applications are also: |
| * Draw the simplified diode equivalent circuit of an NPN transistor and describe the working. | * Draw the simplified diode equivalent circuit of an NPN transistor and describe the working. |
| * Explain the difference between a PNP and NPN transistor. | * Explain the difference between a PNP and NPN transistor. |
| * Draw a circuit each with the respective switch connected to U+ = 5V and ground in such a way that switching through is possible with a voltage between U+ and ground at the base. | * Draw a circuit each with the respective switch connected to $U+ = 5~\rm V$ and ground in such a way that switching through is possible with a voltage between U+ and ground at the base. |
| * Name the respective connections of the transistors in the drawing. | * Name the respective connections of the transistors in the drawing. |
| * What voltage must be applied to the base in each case for the transistor to switch through? | * What voltage must be applied to the base in each case for the transistor to switch through? |
| The collector terminal is at the bottom.| | The collector terminal is at the bottom.| |
| It is a bipolar junction transistor.| | It is a bipolar junction transistor.| |
| To make I_C flow, the voltage U_BE must become positive. | To make $I_\rm C$ flow, the voltage $U_{\rm BE}$ must become positive. |
| </question> | </question> |
| |
| <question title="Which statement(s) about bipolar junction transistors is/are correct?" type="checkbox"> | <question title="Which statement(s) about bipolar junction transistors is/are correct?" type="checkbox"> |
| The current I_C or the voltage U_BC controls the current flow I_B.| | The current $I_\rm C$ or the voltage $U_{\rm BC}$ controls the current flow $I_\rm B$.| |
| The input characteristic of a bipolar junction transistor corresponds to that of a diode.| | The input characteristic of a bipolar junction transistor corresponds to that of a diode.| |
| The disadvantage of the bipolar junction transistor is the continuous current flow required in the conductive state.| | The disadvantage of the bipolar junction transistor is the continuous current flow required in the conductive state.| |
| Due to the body diode, the MOSFET acts in one direction like a diode.| | Due to the body diode, the MOSFET acts in one direction like a diode.| |
| Enrichment type MOSFET are conductive with $U_{\rm GS} =0 ~\rm V$.| | Enrichment type MOSFET are conductive with $U_{\rm GS} =0 ~\rm V$.| |
| In n-channel MOSFETs, holes are the current-carrying charge carriers. | In N-channel MOSFETs, holes are the current-carrying charge carriers. |
| </question> | </question> |
| </quizlib> | </quizlib> |